IEEE Design & Test of Computers September/October 2003 http://www.computer.org/dt/ Features Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs Kenneth M. Butler, Kwang-Ting (Tim) Cheng, and Li-C. Wang Delay Defect Characteristics and Testing Strategies Kee Sup Kim, Subhasish Mitra, and Paul G. Ryan High-Frequency, At-Speed Scan Testing Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, and Nagesh Tamarapalli Achieving At-Speed Structural Test Stephen Pateras AC Scan Path Selection for Physical Debugging Alfred L. Crouch, John C. Potter, and Jason Doege Speed Binning with Path Delay Test in 150-nm Technology Bruce D. Cory, Rohit Kapur, and Bill Underwood Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs Robert Madge, Brady R. Benware, and W. Robert Daasch ITC Watch ITC 2003: Breaking Test Interface Bottlenecks Robert C. Aitken and Gordon W. Roberts ITC Highlights Gordon W. Roberts and Robert C. Aitken Embedded Deterministic Test for Low-Cost Manufacturing Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyzer, and Jun Qian An On-Chip Self-Repair Calculation and Fusing Methodology Darren Anand, Bruce Cowan, Owen Farnsworth, Peter Jakobsen, Steve Oakland, Michael R. Ouellette, and Donald L. Wheater IEEE 1149. 6: A Boundary-Scan Standard for Advanced Digital Networks Bill Eklow, Carl F. Barnhart, and Kenneth P. Parker Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings Peter C. Maxwell ARM Twisting with Sir Robin An Interview with Sir Robin Saxby Departments EIC Message Standards Conference Reports DATC Newsletter TTTC Newsletter The Last Byte --------------------------------------------------- If you wish to be removed from this mailing list, send a message to listserv@computer.org with the following text in the body of the message: unsubscribe dt_subscribers ---------------------------------------------------